1. Field of the Invention
The present invention relates to a circuit for driving a flat display device and, more particularly, to an AC-driven plasma display driving circuit.
2. Description of the Related Art
Conventionally, AC-driven PDPs (Plasma Display Panels) as one of flat display devices are classified into two-electrode type PDPs which perform selective discharge (address discharge) and sustain discharge using two electrodes and three-electrode type PDPs which perform address discharge using a third electrode. The three-electrode type PDPs are further classified into a type with the third electrode formed on a substrate on which the first and second electrodes for performing sustain discharge are laid out and a type with the third electrode formed on another substrate opposite to the substrate of the first and second electrodes.
All types of the above PDP devices are based on the same operation principle. The arrangement of a PDP device in which the first and second electrodes for performing sustain discharge are formed on the first substrate, and the third electrode is formed on the second substrate opposite to the first substrate will be described below.
FIG. 13 is a view showing the overall arrangement of an AC-driven PDP device. In an AC-driven PDP device 1 shown in FIG. 13, a plurality of cells each corresponding to one pixel of a display image are arrayed in a matrix. FIG. 13 shows an AC-driven PDP device having cells arrayed in a matrix with m rows by n columns. The AC-driven PDP 1 also has scanning electrodes Y1 to Yn and common electrodes X, which are formed to run parallel on the first substrate, and address electrodes A1 to Am which are formed on the second substrate opposite to the first substrate so as to run perpendicular to the electrodes Y1 to Yn and X. The common electrodes X are formed in proximities of the scanning electrodes Y1 to Yn in correspondence with them and commonly connected at terminals on one side.
The common terminal of the common electrodes X is connected to the output terminal of an X-side circuit 2. The scanning electrodes Y1 to Yn are connected to the output terminals of a Y-side circuit 3. The address electrodes A1 to Am are connected to the output terminals of an address-side circuit 4. The X-side circuit 2 is formed from a circuit for repeating discharge. The Y-side circuit 3 is formed from a circuit for executing line-sequential scanning and a circuit for repeating discharge. The address-side circuit 4 is formed from a circuit for selecting a column to be displayed. The X-side circuit 2, Y-side circuit 3, and address-side circuit 4 are controlled by control signals supplied from a control circuit 5. That is, a cell to be turned on is determined by the address-side circuit 4 and the line-sequential scanning circuit in the Y-side circuit 3, and discharge is repeated by the X-side circuit 2 and Y-side circuit 3, thereby executing the display operation of the PDP.
The control circuit 5 generates the control signals on the basis of display data D from an external device, a clock CLK indicating the read timing of the display data D, a horizontal sync signal HS, and a vertical sync signal VS and supplies the control signals to the X-side circuit 2, Y-side circuit 3, and address-side circuit 4.
FIG. 14A is a sectional view of a cell Cij as a Pixel, which is in the ith row and jth column. Referring to FIG. 14A, the common electrode X and scanning electrode Yi are formed on a front glass substrate 11. The electrodes are coated with a dielectric layer 12 that insulates the electrodes from a discharge space 17. The dielectric layer 12 is coated with an MgO (magnesium oxide) protective film 13.
On the other hand, the address electrode Aj is formed on a back glass substrate 14 opposite to the front glass substrate 11. The address electrode Aj is coated with a dielectric layer 15, and the dielectric layer 15 is coated with a phosphor 18. Ne+Xe Penning gas is sealed in the discharge space 17 between the MgO protective film 13 and the dielectric layer 15.
FIG. 14B is a view for explaining a capacitance Cp of the AC-driven PDP. As shown in FIG. 14B, in the AC-driven PDP, capacitive components Ca, Cb, and Cc are present in the discharge space 17, between the common electrode X and the scanning electrode Y, and in the front glass substrate 11, respectively. A capacitance Cpcell per cell is determined by the sum of the capacitive components (Cpcell=Ca+Cb+Cc). The sum of capacitances Cpcell of all cells in the panel corresponds to the panel capacitance Cp.
FIG. 14C is a view for explaining light emission of the AC-driven PDP. As shown in FIG. 14C, stripe-shaped red, blue, and green phosphors 18 are laid out and applied to the inner surfaces of ribs 16. The phosphors 18 are excited by discharge between the common electrode X and the scanning electrode Y so as to emit light.
FIG. 15 is a timing chart showing a conventional method of driving an AC-driven PDP. FIG. 15 shows one of a plurality of subfields of one frame. One subfield is divided into a reset period comprised of a full write period and full erase period, an address period, and a sustain discharge period.
In the reset period, all the scanning electrodes Y1 to Yn are set at the ground level (0 V), and simultaneously, a full write pulse having a voltage Vs+Vw (about 400 V) is applied to the common electrodes X. At this time, all the address electrodes A1 to Am have a potential Vaw (about 100 V). Consequently, discharge occurs in all cells of all display lines to generate wall charges independently of the preceding display state.
Next, the potentials of the common electrodes X and address electrodes A1 to Am change to 0 V. As the voltage of wall charges themselves exceeds the discharge start voltage in all cells, discharge starts. In this discharge, no wall charges are formed because the electrodes have no potential difference. Space charges cause so-called self-erase discharge and neutralize by themselves to end the discharge. With this operation, all cells in the panel are set in a uniform state free from wall charges. The reset period acts to set all cells in the same state independently of the ON/OFF state of each cell in the preceding subfield. This makes it possible to stably perform the subsequent address (write) discharge.
In the address period, address discharge is line-sequentially performed to turn on/off each cell in accordance with display data. First, a voltage of −Vy level (about −150 V) is applied to the scanning electrode Y1 corresponding to the first display line, and a voltage of −Vsc level (about −50 V) is applied to the scanning electrodes Y2 to Yn corresponding to the remaining display lines. At the same time, an address pulse having a voltage Va (about 50 V) is selectively applied to the address electrode Aj (j is an arbitrary number, 1≦j≦m) corresponding to a cell which should cause sustain discharge, i.e., a cell to be turned on in the address electrodes A1 to Am.
As a result, discharge occurs between the scanning electrode Y1 and the address electrode Aj of the cell to be turned on. With this priming (pilot flame), discharge between the scanning electrode Y1 and the common electrode X having a voltage Vx (about 50 V) immediately starts. With this discharge, wall charges in an amount enough for the next sustain discharge are accumulated on the surface of the MgO protective film 13 on the common electrode X and scanning electrode Y1 of the selected cell. For the scanning electrodes Y2 to Yn corresponding to the remaining display lines as well, the voltage of −Vy level is sequentially applied to a scanning electrode corresponding to a selected cell, and the voltage of −Vsc level is applied to the scanning electrode corresponding to each of remaining, unselected cells. With this processing, new display data is written in all display lines.
In the subsequent sustain discharge period, a sustain pulse having a voltage Vs (about 200 V) is alternately applied to the scanning electrodes Y1 to Yn and common electrodes X to perform sustain discharge so that an image of one subfield is displayed. The luminance of the image is determined by the length of the sustain discharge period, i.e., the number of times of application or the frequency of sustain pulses.
In the AC-driven PDP, a voltage Vf at which gas discharge starts on the surface between the common electrode X and the scanning electrode Y is generally 220 to 260 V. The scanning electrode Y is an arbitrary one of the above-described scanning electrodes Y1 to Yn. In the address period, for example, a voltage is applied between the address electrode A and the scanning electrode Y of a cell to be displayed such that gas discharge occurs. This triggers discharge between the common electrode X and the scanning electrode Y so as to generate wall charges on the common electrode X and scanning electrode Y in that cell.
Next, in the sustain discharge period, |Vs+Vwall| is increased to Vf or more by the sustain pulse voltage Vs applied between the common electrode X and the scanning electrode Y together with wall charges Vwall generated in the address period, thereby performing gas discharge. The value of the voltage Vs does not exceed the discharge start voltage Vf, and a voltage value that satisfies |Vs|<|Vf|<|Vs+Vwall| is defined as Vs.
When gas discharge occurs between the common electrode X and the scanning electrode Y, wall charges on the common electrode X and the scanning electrode Y in that cell obtain an opposite polarity to stop the gas discharge. The sustain pulse voltage Vs having an opposite polarity is applied between the common electrode X and the scanning electrode Y, thereby performing gas discharge again using the wall charges formed on the common electrode X and the scanning electrode Y. When the above operation is repeated, gas discharge can be repeatedly performed.
However, to drive an AC-driven PDP by the above-described drive method, drive voltages according to the timing chart shown in FIG. 15 must be applied to the respective electrodes, and each element of the AC-driven PDP driving circuit must have a high breakdown voltage. Especially, a circuit for applying a full write pulse voltage Vs+Vw (about 400 V) shown in FIG. 15 to the X-electrode must be constructed using elements having a very high breakdown voltage corresponding to the full write pulse voltage. For this reason, an expensive and large switch element such as an FET must be used to ensure a sufficient breakdown voltage. This complicates the circuit arrangement and considerably increases the manufacturing cost.
As a solution to this problem, an AC-driven PDP driving method has been proposed, in which in performing discharge between the electrodes of an AC-driven PDP, a positive voltage is applied to one electrode, and a negative voltage is applied to the other electrode, thereby causing discharge between the electrodes using the potential difference between them.
FIG. 16 is a circuit diagram showing the arrangement of a driving circuit for implementing a method of driving an AC-driven PDP which performs discharge between electrodes using the potential difference between them. Referring to FIG. 16, a load 20 is the total capacitance of a cell formed between one common electrode X and one scanning electrode Y. The common electrode X and scanning electrode Y are formed on the load 20.
Switches SW1 and SW2 of a circuit on the common electrode X side are connected in series between the power supply line of a voltage (Vs/2) supplied from a power supply circuit (not shown) and the ground (GND) An interconnection node between the two switches SW1 and SW2 is connected to one terminal of a capacitor C1. A switch SW3 is connected between the GND and the other terminal of the capacitor C1.
Switches SW4 and SW5 are connected in series between the two terminals of the capacitor C1. An interconnection node between the two switches SW4 and SW5 is connected to the common electrode X of the load 20. A switch SW6 applies a voltage Vx′ (=Vs/2+Vx) to the common electrode X. The switch SW6 is connected in series between the power supply line of the voltage Vx′ supplied from a power supply circuit (not shown) and a second signal line OUTB.
A diode D4 flows a current from the GND to the load 20 through the common electrode X at a timing when the positive voltage (+Vs/2) applied to the scanning electrode Y is returned to the ground level. A diode D5 flows a current from the load 20 to the GND through the common electrode X at a timing when the positive voltage (+Vs/2) is applied to the scanning electrode Y.
Switches SW1′ and SW2′ of a circuit on the scanning electrode Y side are connected in series between the power supply line of the voltage (Vs/2) supplied from the power supply circuit (not shown) and the ground (GND). An interconnection node between the two switches SW1′ and SW2′ is connected to one terminal of a capacitor C2. A switch SW3′ is connected between the GND and the other terminal of the capacitor C2.
A switch SW4′ connected to the one terminal of the capacitor C2 is connected to the cathode of a diode D7. The anode of the diode 07 is connected to the other terminal of the capacitor C2. A switch SW5′ connected to the other terminal of the capacitor C2 is connected to the anode of a diode D6. The cathode of the diode D6 is connected to the one terminal of the capacitor C2.
One terminal of the switch SW4′ connected to the cathode of the diode D7 and one terminal of the switch SW5′ connected to the anode of the diode D6 are connected to the load 20 through a scan driver 21. The scan driver 21 has a series circuit of two transistors. An interconnection node between the two transistors is connected to the scanning electrode Y of the load 20. The scan driver 21 is prepared for each of a plurality of display lines of the PDP.
A switch SW7 applies to the scanning electrode Y a voltage Vw′ (=Vs/2+Vw) for executing a write in all cells of the PDP. The switch SW7 is connected in series between the power supply line of the voltage Vw′ supplied from a power supply circuit (not shown) and a fourth signal line OUTB′. The switch SW7 has a resistor R1. The applied voltage is continuously changed by the function of the resistor R1 along with the elapse of time, thereby applying the voltage Vw′ to the scanning electrode Y.
Switches SW8 and SW9 give a potential difference of (Vs/2) across the scan driver 21 during the address period. That is, during the address period, the switches SW2′ and SW8 are turned on to set the voltage on the upper side of the scan driver 21 at the ground level. In addition, the switch SW9 is turned on to apply a negative voltage −Vy supplied from the connected power supply circuit to the lower side of the scan driver 21 through the fourth signal line OUTB′. In this way, in outputting the scanning electrode Y corresponding to a line-sequentially selected display line, the negative voltage −Vy is applied to the scanning electrode Y by the scan driver 21.
After the voltage Vw′ is applied to the scanning electrode Y in the reset period, a ramp wave generation circuit 22 applies the voltage −Vy to the scanning electrode Y to perform erase operation for all cells of the PDP. The ramp wave generation circuit 22 has a switch SW11 connected in series between the power supply line of the voltage −Vy supplied from the power supply circuit (not shown) and the upper side of the scan driver 21. The switch SW11 has a resistor R2. By the function of the resistor R2, the applied voltage is continuously changed from the voltage Vw′ to the voltage −Vy along with the elapse of time.
FIG. 17 is a circuit diagram showing the detailed circuit arrangement of the ramp wave generation circuit 22. Referring to FIG. 17, the same reference numerals as in FIG. 16 denote parts having the same functions as in FIG. 16, and a repetitive description will be omitted.
Referring to FIG. 17, a photocoupler 23 converts the reference level of a control signal for the switch SW11, which is supplied from a drive signal generation circuit (not shown), from the ground level to the −Vy potential level, i.e., the reference level of the switch SW11. A MOS driver 24 for driving the switch SW11 shifts the level of the control signal for the switch SW11, which is level-converted by the photocoupler 23, to the gate drive level of the switch SW11 and supplies the control signal to the switch SW11. The MOS driver 24 has two transistors Tr11 and Tr12. The transistors Tr11 and Tr12 are ON/OFF-controlled in accordance with the control signal for the switch SW11, which is level-converted by the photocoupler 23, thereby supplying the drive voltage for the switch SW11 to the switch SW11.
A power supply circuit 26 generates the voltage −Vy as the reference potential of each element of the ramp wave generation circuit 22. A floating power supply 25 generates a voltage Ve using the potential −Vy generated by the power supply circuit 26 as a reference level and supplies the voltage Ve. The voltage Ve using the potential −Vy as a reference level is supplied to the output portion (light-receiving element) of the photocoupler 23 and the MOS driver 24. That is, the floating power supply 25 supplies the gate voltage of the switch SW11.
FIG. 18 is a timing chart showing an example of an AC-driven PDP driving method using the driving circuit shown in FIGS. 16 and 17. FIG. 18 shows one of a plurality of subfields of one frame, as in FIG. 15 described above. For the description of FIG. 18, assume that charges corresponding to the voltage (Vs/2) are accumulated in the capacitor C1 on the common electrode X side and in the capacitor C2 on the scanning electrode Y side by processing of the preceding subfield.
In the reset period, first, on the common electrode X side, the switches SW2 and SW5 are turned on, and the switches SW1, SW3, SW4, and SW6 are turned off. The voltage of the second signal line OUTB is reduced to (−Vs/2) in accordance with the charges accumulated in the capacitor Cl. The voltage is output to an output line OUTC through the switch SW5, so the negative voltage (−Vs/2) is applied to the common electrode X.
Simultaneously, on the scanning electrode Y side, the switch SW7 is turned on, and the switches SW1′ to SW5′, SW8, SW9, and SW11 are turned off. The positive voltage Vw′ (=Vs/2+Vw) is applied to all the scanning electrodes Y. With this operation, a potential difference between the common electrode X and scanning electrode Y have a potential difference corresponds to the full write pulse voltage (Vs+Vw) shown in FIG. 15. The positive voltage (Vs/2+Vw) applied to the scanning electrode Y continuously changes along with the elapse of time. In the following description, unlike a waveform, such as a pulse applied to the electrode in the sustain discharge period, whose voltage changes in a short time, a ramp waveform whose voltage continuously changes in a sufficiently long time along with the elapse of time will be called a “ramp wave”.
When such a ramp wave is applied, discharge sequentially occurs in cells where the potential difference between the Y-electrode and the common electrode X has reached the discharge start voltage during the rise of the ramp wave. Actually, discharge occurs in each cell at an optimum voltage (voltage almost equal to the discharge start voltage)
Next, on the common electrode X side, the switch SW5 is turned off, and the switch SW4 is turned on to set the voltage of the common electrode X at the ground level (0 V). After that, on the common electrode X side, the switch SW2 is turned off, and the switches SW5 and SW6 are turned on, thereby applying the positive voltage Vx′ (Vs/2+Vx) to the common electrode X.
On the scanning electrode Y side, the switch SW7 is turned off, and the switch SW11 is turned on, thereby applying to the scanning electrode Y a ramp wave whose voltage gradually drops and finally reaches the negative voltage (−Vy). The negative voltage (−Vy) is about (−Vs/2). As the voltage of wall charges themselves exceeds the discharge start voltage in all cells, discharge starts. At this time as well, weak discharge occurs between the common electrode X and the scanning electrode Y in accordance with application of the ramp wave, so the accumulated wall charges are erased with some exceptions.
In the address period, address discharge is line-sequentially performed to turn on/off each cell in accordance with display data. At this time, on the common electrode X side, the switch SW2 is turned off, and the switches SW5 and SW6 are turned on, thereby applying the voltage Vx′ to the common electrode X. For the scanning electrodes Y, the switches SW2′, SW8, and SW9 are turned on to apply a voltage of (−Vs/2) level to each scanning electrode Y corresponding to a line-sequentially selected display line. In addition, the switches SW2′ and SW8 are turned on to apply a voltage of the ground level to each unselected scanning electrode Y.
At this time, an address pulse having the voltage Va is selectively applied to the address electrode Aj in the address electrodes A1 to Am, which corresponds to a cell which should cause sustain discharge, i.e., a cell to be turned on. As a result, discharge occurs between the address electrode Aj of the cell to be turned on and the line-sequentially selected scanning electrode Y. With this priming (pilot flame), discharge between the common electrode X and the scanning electrode Y immediately starts. Wall charges in an amount enough for the next sustain discharge are accumulated on the MgO protective film on the common electrode X and scanning electrode Y of the selected cell.
When a ramp wave is applied in the full erase period in the reset period to perform weak discharge, discharge between the address electrode Aj and the scanning electrode Y is started by the potential difference (Va+Vs/2) between the electrodes. Since wall charges on the scanning electrode Y are not completely erased in the reset period and some wall charges are left, the discharge start voltage can be obtained by the residual wall charges and the actually applied voltage, and discharge starts.
In the sustain discharge period, when the switches SW6 to SW9 and SW11 are turned off, and the switches SW1 to SW5 on the common electrode X side and the switches SW1′ to SW5′ on the scanning electrode Y side are ON/OFF-controlled at appropriate timings, the voltage changes in an order of Vs/2→0 V→−Vs/2→0 V→Vs/2 . . . , so voltages with different phases are applied to the common electrode X and the scanning electrode Y of each display line. Hence, the potential difference between the common electrode X and the scanning electrode Y of each display line becomes equal to the sustain pulse voltage shown in FIG. 15, sustain discharge is performed, and an image of one subfield is displayed. During the sustain discharge period, the potentials of the address electrodes A1 to Am are kept at the ground level as the intermediate potential between the common electrode X and the scanning electrode Y.
In this way, when a positive voltage is applied to one electrode, and a negative voltage is applied to the other electrode using the driving circuit shown in FIGS. 16 and 17, a potential difference corresponding to each pulse shown in FIG. 15 can be generated between the electrodes. The breakdown voltage of each element of the driving circuit can be made lower as compared to a case wherein an AC-driven PDP is driven in accordance with the timing chart shown in FIG. 15.
In addition, when a ramp wave is applied in the full erase period in the reset period to perform weak discharge such that wall charges on the scanning electrode Y are not completely erased, and some wall charges are left, discharge between the address electrode Aj and the scanning electrode Y in the address period can be started by a potential difference (Va+Vs/2) lower than the conventional potential difference (Va+Vy). Hence, a cell to be turned on in the sustain discharge period can be accurately selected.
However, in the proposed PDP driving circuit, power supply circuits for externally supplying the voltage −Vy and the voltage −Vey must be separately arranged, as shown in FIG. 17. Furthermore, since the reference level of the control signal supplied to the ramp wave generation circuit 22 and that of the signal for driving the switch SW11 are different, a signal transmission circuit for converting the signal input with reference to the GND level into a signal with reference to −Ve, such as a photocoupler, must be prepared, and the circuit arrangement becomes very complex.